1. Field of the Invention
The present invention relates to methods of manufacturing semiconductor devices, and more particularly to forming high quantum efficiency (QE) charge coupled devices (CCDs).
2. Related Art
Charged coupled device (CCD) sensors have been utilized in various demanding sensing applications such as high end visible light imaging, UV imaging, X-Ray imaging, spectroscopy, and more. However conventional CCDs suffer from poor sensitivity to short wavelength bands such as blue, UV, and soft X-Ray. This problem is caused by the absorption of short wavelength photons by the polysilicon layers utilized in forming gate structures in a CCD. The poor sensitivity to certain wavelength bands is manifested as a reduction in the total Quantum Efficiency (QE) of the CCD.
To overcome the decreased sensitivity problem, several methods were developed and have been used for producing higher QE CCD sensors. The prior art addressing the reduced QE issue includes the following.
Back Thinned CCD (also referred to as Back Illuminated CCD) technology thins the back side of the CCD via a chemical etching or grinding process in order to be able to illuminate the sensor through the back and not through the front side that contain the blocking gate structures. This approach provides high QE and fill factor (FF). However, Back Thinned CCD is a costly process. The process of thinning is both expensive and poor yielding which further increases the device price.
CCD with transparent gate structure technology provides a method of forming the gate structures in the CCD from transparent material such as indium-tin-oxide (ITO). The transparent gate structure allows photons to enter the photosensitive silicon of the CCD unimpeded. A disadvantage to this approach is that it suffers from non-uniformity caused by the variation of the ITO layer thickness across the sensor array that is due to chemical mechanical polishing (CMP) used for achieving the required electrical isolation between adjacent ITO gates. Charge Transfer Efficiency (CTE) is also reduced due to fixed electrostatic charges which happen in overlying insulating layers of the device and cause small potential variations below the insulating gap between the CCD electrodes. Thus creating a potential pocket (or well) in the region beneath the electrode gap introduces charge transfer inefficiency.
CCD with U-shaped gates employs adjacent, non-overlapping U-shaped electrodes within the CCD. This prior art addresses the non-uniformity and decreased CTE problems of the ITO CCD. Since the gate electrodes are of a substantially U-shaped geometry, it shields the charge transfer channel from the effects of the fixed charge (that creates the “pockets” as explained previously). However, CCD with U-shaped gates, while addressing the problems of CCD with ITO Gate, is afflicted by reduced full well due to much reduction in the gate area. This manifests as lower dynamic range.
Deposition of material sensitive to short wavelength deposits materials such as UV sensitive organic phosphor coatings (e.g., Coronene or Lumagen). UV sensitive organic phosphor coating converts UV photons to the visible (i.e., increasing wavelength) and thus allows them to be sensed by the photosensitive silicon of the CCD. However, this approach suffers from increased pixel-to-pixel crosstalk due to scattered light emitted from the phosphor layer since there is a gap between the short wavelength sensitive coating, such as Lumagen and the silicon surface. This will reduce image sharpness (i.e., lower the spatial frequency response also referred to as modulation transfer function or MTF).
Virtual-phase CCD with single phase timing technology addresses the QE problem of the front illuminated CCD by eliminating at least one of the gate structures and thus leaving part of the pixel area uncovered by polysilicon layers associated with the gate. Thus a larger part of the CCD pixel is exposed, thereby allowing photons to enter the photosensitive silicon of the CCD unimpeded. In order to facilitate one of the charge transfer phases employed by the CCD, a virtual electrode is formed by means of appropriate implants. A drawback to this technology is that it also suffers from charge transfer efficiency (CTE) problems due to spurious potential pockets which trap charges in the signal transfer channel. The potential pockets are the result of unavoidable small misalignment of implants for potential well shape. Adding background charge in order to fill the pockets may increase CTE but inevitably increases noise (i.e., shot noise of the added background charge).
Open-pinned-phase (OPP) CCD with dual-phase timing technology addresses the QE of the front-illuminated CCD by eliminating one gate structure and thus also leaving part of the pixel area uncovered by polysilicon layers associated with the gate. Thus, a larger part of the CCD pixel is exposed (also referred to as “open”), hence allowing photons to enter the photosensitive silicon of the CCD unimpeded. In order to facilitate charge transfer employed by the CCD dual gate structure is utilized. However, OPP CCD with dual-phase timing suffers from slow charge transfer process, thus precluding it from usage in applications where reasonable frame rates are of interest. Since the transfer through the open phase is unaided by electric or fringing fields and controlled primarily through thermal diffusion for smaller charge packets, the CTE at higher speeds will be unacceptable for low signals, and poor for even larger packets that are helped by self induced drift.
Accordingly, it is desirable to have a CCD that can provide very high Quantum Efficiency at a reasonable price for high frame rate and other demanding application without the disadvantages discussed above associated with prior art CCDs or imaging sensors.